Conceptual Design of Multichip Modules and Systems treats activities which take place at the conceptual and specification level of the design of complex multichip systems. These activities include the formalization of design knowledge (information modeling), tradeoff analysis, partitioning, and decision process capture. All of these functions occur prior to the traditional CAD activities of synthesis and physical design. Inherent in the design of electronic modules are tradeoffs which must be understood before feasible technology, material, process, and partitioning choices can be selected. The lack of a complete set of technology information is an especially serious problem in the packaging and interconnect field since the number of technologies, process, and materials is substantial and selecting optimums is arduous and non-trivial if one truly wants a balance in cost and performance. Numerous tradeoff and design decisions have to be made intelligently and quickly at the beginning of the design cycle before physical design work begins. These critical decisions, made within the first 10% of the total design cycle, ultimately define up to 80% of the final product cost. Conceptual Design of Multichip Modules and Systems lays the groundwork for concurrent estimation level analysis including size, routing, electrical performance, thermal performance, cost, reliability, manufacturability, and testing. It will be useful both as a reference for system designers and as a text for those wishing to gain a perspective on the nature of packaging and interconnect design, concurrent engineering, computer-aided design, and system synthesis.
Conceptual Design of Multichip Modules and Systems treats activities which take place at the conceptual and specification level of the design of complex multichip systems. These activities include the formalization of design knowledge (information modeling), tradeoff analysis, partitioning, and decision process capture. All of these functions occur prior to the traditional CAD activities of synthesis and physical design.
The platform-centric SoC method is aimed at the design of today's SoC systems with emphasis on real-time, embedded systems. The approach provides a guideline and an SoC design environment that promotes an integration of state-of-the-art tools and techniques necessary for the development of the systems. It renders a new and better perspective towards co-design approaches, while also raising a level of design abstraction. Because the configurable platform objects are designed off-cycle, they contribute to a general improvement in development time. By incorporating their usage, the overall method strikes a balance between total design flexibility and minimal time-to-market.
In Chapter 1, challenges in the co-design of SoCs are introduced. The chapter briefly describes the technical challenges facing system developers and introduces a proposed solution to the problem. The remainder of this book presents a more thorough examination on the problem and the proposed approach.
Chapter 2 describes the proposed platform-centric SoC design method in detail. It illustrates the design flow and discusses each main step in the design process. Definition of a platform as originally defined by Sabbagh 96], as well as the platform-based and platform-centric design approaches, are presented. The chapter concludes by comparing the proposed approach with previous related work.
Chapter 3 lays out the technological background for the proposed SoC design method. Whereas the platform technology is discussed in Chapter 2, this chapter gives an overview of the other two fundamental technologies: the Unified Modeling Language (UML) and the Extensible Markup Language (XML). The chapter begins with an introduction to UML as a modeling tool very well perceived within the software engineering community. It is followed by a discussion on an attempt by the Object Management Group (OMG) to empower UML for the development of real-time embedded software - an effort which will eventually culminate in a design framework known as the UML Profile for Schedulability, Performance, and Time Specification 29]. Thereafter, an overview of XML and a few other related internet technologies ensue.
Chapter 4 outlines the structure of the library of platform objects (LPO), as well as furnishes a comprehensive guideline and requirements specification that a platform object must possess in order to be scalable and compatible with the proposed approach. Essential elements for each platform object, e.g. architecture blueprint, XML-based self-described modules, platform managing tool, etc., are also discussed in detail.
Chapter 5 provides a detailed treatment of UML extensions for the development of real-time embedded systems. The chapter starts with a layout of the Co-design Modeling Framework (CMF) hierarchy that encompasses five other sub-profiles - the generic utility profile (PCUprofile), the Exception Modeling profile (EMprofile), the Interrupt Modeling profile (IMprofile), the Synthesizable Hardware Description Language profile (SHDLprofile), and the Architecture Blueprint profile (ABprofile). Each of these profiles furnishes a design framework that is specifically tailored for the proposed approach, and may be able to meet with the challenges posed by the design and test of real-time embedded SoC-based systems. The chapter, then, proceeds to discuss the domain concept for each sub-profile, followed by the description of the corresponding stereotypes.
Chapter 6 applies the platform-centric SoC design method, using the CMF profile in UML, to the development of a simplified digital camera system so as to demonstrate the use and the robustness of the proposed approach. Specifically, the NiOS development board is used to mimic the digital camera system where raw image data are read from a charge-coupled device (CCD), and then JPEG encoded and stored into memory. The chapter begins with an overview of the Altera's NiOS system, followed by the actual system development process that explicitly demonstrates the use of the proposed approach. A quantitative evaluation is then presented that compares the development cost of the proposed platform-centric SoC design method against some alternative approaches using cost estimation models and tools.
Chapter 7 concludes the book with a summary and a discussion of future directions for this effort on platform-based design.
The essential problem in entrepreneurship is improving the performance of entrepreneurs. The most important theories will be the ones that most enable us to predict and then ultimately influence entrepreneurial performance. This book develops a new and more accurate theory of entrepreneurial performance based in entrepreneurial creativity. The field of entrepreneurship has a long tradition of expecting entrepreneurial performance to be influenced by creativity, tracing back even before the pioneering work of Joseph Schumpeter (1883 to 1950), who defined entrepreneurship as creative-destruction creating the new by supplanting or destroying the old. Subsequently, psychologist Robert Sternberg defined creativity as broadly encompassing creative aspects of personality, motivation, intellect, thinking style and relevant knowledge. Using Sternberg s definition of creativity, the authors reviewed the evidence directly linking entrepreneurial creativity and entrepreneurial performance, concluding that the linkage is both statistically and practically significant. In order to scientifically tie entrepreneurship to creativity the book pursues a number of major objectives: In parts one and two, the authors remind us of our scientific challenge in the light of the depressing levels of performance typically to be found in the real world of entrepreneurship and explores the limitations of the dominant paradigms driving research in the field of entrepreneurship today. In part three, they bring together existing evidence to demonstrate the predictive and explanatory powers of creativity in relation to entrepreneurship. In part four, they further explore correlations between creativity and entrepreneurial performance at the individual and macro or society, levels. In summary, the book offers a bold predictive theory linking entrepreneurial creativity to entrepreneurial performance, however neither as boldly as a definitional linkage nor as timidly as one in a hundred or so factors potentially explaining entrepreneurial performance. This result is a general scientific theory that offers a serious challenge to entrepreneurial scholars who are pursuing other means for understanding the causality of entrepreneurial performance."
Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
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